Rms sensing apparatus

ABSTRACT

An RMS sensing device wherein a first electrical quantity proportional to the square of at least a portion of an electrical quantity to be measured is established, by passing the desired portion of the quantity to be measured through two p-n junctions in series, and thereafter using the first electrical quantity to control the flow of current through an output circuit comprising two more p-n junctions connected in series and including a capacitor connected in shunt with a selected one of the p-n junctions of the output circuit to eliminate the alternating current component from the selected p-n junction whereby the direct current flowing through the output circuit is a direct measurement of the RMS of the quantity which is being measured.

Unlted States Patent 11 1 [111 3,743,949

Engel et al. July 3, 1973 [54] RMS SENSING APPARATUS 3,398,297 8/1968Huen 328/144 [75] Inventors: Joseph C. Engel; Robert T. Elms,

both of M Onroevme Pa Prir nary Examiner-John W. Huckert AssistantExammer-R. E. Hart 1 1 Assigneez ngh Electric C rp Attorney-A. T.Stratton. John L. Stoughton et 21].

Pittsburgh, Pa.

[22] Filed: July 23, 1971 [57] ABSTRACT [21] App]. No; 165,462 An RMSsensing device wherein a first electrical quantity proportional to thesquare of at least a portion'of an electrical quantity to be measured isestablished, by [52] 11.8. CI. 328/144, 235/1325 passing the desiredportion of the quantity to be [5 Sured h g two p junctions in Series,and ere [58] Field of Search 328/144, 145, using the first electricalquantity to control the flow 235/158 1934935 324/132 of current throughan output circuit comprising two more p-n junctions connected in seriesand including a [56] References cued capacitor connected in shunt with aselected one of the UNITED STATES PATENTS p-n junctions of the outputcircuit to eliminate the al- 3,423,578 1/1969 Platzer 235/1935 ternatingcurrent component from the selected p-n 3,152,250 10/1964 Platzer235/193 junction whereby the direct current flowing through 31064119211/1962 Schwarzlanderw 323/144 the output circuit is a directmeasurement of the RMS 3,070,302 12/1962 Fluegel 328/144 of the quantityWhich is being measured 3,281,689 10/1966 Schneider 328/144 28 Claims, 3Drawing Figures N f 8 VI RMS SENSING APPARATUS BRIEF SUMMARY OF THEINVENTION This invention is directed to a transducer which uses aminimum of elements for providing a direct current output signal whichis directly proportional to the RMS value of the alternating quantityapplied to the input ,terminals-of the transducer which comprises afirst set of p-n junctions providing a log output which is proportionalto the square of the input signal and apparatus for taking the antilogof this output signal with a network similar to the network whichprovided the log signal except that the antilog network is provided withmeans for bypassing the alternating current components of the currentflowing in the outputs circuit around one of the p-n junctions of theantilog circuit.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a schematic diagram showing atransducer embodying the invention;

FIG. 2 is a schematic diagram showing a modified form transducerembodying the invention; and,

FIG. 3 is a schematic diagram showing a still further modified form oftransducer embodying the invention.

DETAILED DESCRIPTION Referring to the drawings by characters ofreference and more particularly to FIG. I, the numeral 1 indicatesgenerally a current transformer having a primary winding connected to beenergized by an alternating electrical current quantity, the RMS valueof which is to be determined. The transformer 1 has a secondary oroutput winding 4 connected through a full wave rectifier bridge 6 topositive and negative buses 8 and 10.

A first pair of transistors 12 and 14, arranged with their basesconnected to their collectors whereby they operate as rectifiers, areconnected in series to provide a log potential generating circuit whichis connected between the buses 8 and 10. These transistors 12 and 14,which will sometimes hereinafter be referred as diodes 12 and 14, eachinclude a p-n junction through which current flows between the positivebus 8 and the negative bus 10. As is known in the art, a pmsemiconductor junction exhibits a logarithmic relationship between themagnitude of the current flowing therethrough and the magnitude of thevoltage established thereacross. Therefore the magnitude of the voltageestablished between the buses 8 and due to current flow through theprimary winding 2 of the current transformer 1 will have a magnitudewhich is directly proportional to the log of the square of thealternating quantity of the current slowing through the winding 2.

An output circuit 18 is energized from a source of unidirectionalpotential illustrated as a battery 20. The positive terminal of source20 is connected through a direct current indicating instrument 21 to anantilog circuit 22. The antilog circuit comprises the collector andemitter of a transistor 24, and the collector and emitter of atransistor 26. The antilog circuit is in turn connected to the negativeterminal of the battery 20. The base of the transistor 26 is connectedto the collector thereof whereby the transistor 26 acts as a p-njunction diode. A capacitor 28 is connected in shunt with thecollector-emitter circuit of the transistor 24. The capacitor 28 is ofsufficient capacity to cause the alternating current portion orcomponent of the current flowing in the antilog circuit 22 to circulatesolely in the remainder of the output circuit 18 is a direct current ofa magnitude proportional to the RMS of the alternating current beingmeasured. A suitable capacitor 28 would have upwardly of 10 mfd for a60Hz applied current to the transformer 1 whereby the sum of thechanging current of the capacitor 28 and the antilog current through thetransistor 24 is substantially constant over each half cycle of aconstant applied current to the transformer 1.

The base of the transistor 24 is connected to the positive bus 8 and theemitter of the transistor 26 is connected to the bus 10, whereby thebase drive current in the transistor 24 flows in accordance with thepotential established across the log potential generating circuit 16.The output circuit is calibrated by a variable resistor 21A shuntedaround the instrument 21 which compensates for the differences in themultiplying factors of the devices 12, 14, 24 and 26.

As will be proved mathematically below, the direct current component ofthe pulsating current flowing through the output circuit 18 or 18' has amagnitude which is directly proportional to the RMS magnitude of thecurrent flowing in the primary to the current transformer l.

As illustrated in FIG. 2, the buses 8 and 10 may be energized inaccordance with the log of the square of the voltage applied to theinput terminal 30 and 32 since the current flow through the primarywinding 2 is controlled by a resistor 34 and will vary as a function ofthe magnitude of the voltage at the terminals 30-32. In the FIG. 2arrangement the capacitor 28 is connected in shunt with thecollector-emitter circuit of the transistor 26 and its capacity is largeto pass all of the alternating component of the current flowing throughthe antilog circuit 22. In the form of the invention of FIG. 2, thecapacitor 28' should have higher capacity than the capacitor 28 and inmost instances will be upwards of 50 mfd. This is because of the lowereffective impedance of the discharge circuit for the capacitor 28'. InFIG. 2 the current flow through the device 26 will be substantiallyconstant and the current through the remainder of the output circuit 18'will have an alternating component. With a damped DC instrument 21, theAC "component will not be indicated and the instrument 21 will read thetrue RMS of the current through the transformer which in FIG. 2 is ameasure of the RMS of the voltage applied to terminals 30 and 32.

The letter x is equal to the instantaneous magnitude of the pulsatinginput quantity supplied by the winding 4, the letter i is equal to theinstantaneous magnitude of the DC quantity or component flowing in theoutput circuit 18, the letter i is equal to the instantaneous magnitudeof the ac quantity or component in the output circuit 18, and the letteri is equal to the instantaneous magnitude of the total of the ac and dcquantities flowing in the output circuit 18.

By definition, the alternating component i of a periodic quantity is aquantity which when averaged throughout the complete period T of therecurring periodic quantity of zero value. In an instance in which asine wave is applied to the transformer winding 2, the complete period Tof the recurring components supplied by the full wave rectifier will beequal to one half the period 21r of the supplied sine wave wt. In theevent the wave supplied to the transformer is not symmetrical about itszero axis but otherwise repeats itself, the full or complete period T ofthe alternating component would be the same as the period of thesupplied wave. Also by definition x, of a periodic quantity is aquantity which varies in magnitude but not polarity during the period Tas above defined.

The capital letter with the subscript RMS added represents the RMS valueof the quantity represented by the same lower case letter. A multiplyingconstant which depends upon the area of the p-n junction is representedby the letters k k k and k.,. The base of the log depends upon thedoping of the p-n junction. The doping of like p-n junction is heldrather closely and all of the p-n junctions may be assumed to be thesame so that the log base, not indicated, is the same for all of the p-njunctions. The area for the four p-n junctions will normally besubstantially alike so that the error produced thereby will be nogreater than :5 percent. This small error may be compensated by theproper adjustment of the calibrating resistor 21A.

The mathematical solution for a pulsating input quantity having a timeperiod T is as follows:

log (K; i log (K,, i) log (K' x) log (K x) (1 log (K K i i) log (K K x 2n i: l zl a 4) X2 K2 l z/ ns 4) i i= K x I 6 x x, x,, 7

because no dc component can be supplied by the windmg therefore 0 RMS(I?) With modern transistors, the value of K approaches 1 and can beexpected to remain within i005 which means that i equals the RMS valueof the quantity applied to the input transformer l with an error notgreater than i 2.2 percent which error can be compensated for byadjusting the calibrating resistor 21A.

FIG. 3 illustrates a device which functions as above described but whichembodies a current splitting network which considerably simplifies thedesign of the current transformer. This is because only micro amperesare required for the solid state devices l2, 14, 24

and 26. Assuming that 200 microamperes is the current required for thedevices 12 and 14 and a single turn primary winding 2A carrying 10amperes is used, the secondary winding 4A would require 50,000 turns. Itis of course possible to build such a transformer but it would be bulkyand expensive With a current splitting device, the current transformerwill be smaller even though it delivers more amperes. For example,assuming a turns ratio as set forth in FIG. 3 wherein four turns of the20 turn primary is used with 8,000 turns on the secondary a current flowof 10 ampere in the four turn primary will cause 5,000 microamperes toflow in the secondary winding 4A. This current is split between twopaths 16' and 17' with 200 microamperes flowing through path 16 and thebalance flowing through path 17'. The path 16 includes a resistor R1, avariable resistor R2, the emitter-collector circuit of a transistor T-lland the devices 12 and 14. The path 17 includes a diode D1, resistor R3,a resistor R4 and a Zener diode D2. A positive bus 40 extends from thebus 8 through the diode D1 and resistor R3 and is maintained at a fixedpotential above the negative bus 10 by a Zener diode D3 shunted by acapacitor C1.

The indicating instrument 21 has one terminal connected to the bus 40and its other terminal connected through a suitable instrument shunt S1,resistors R5 and R6 of a filter F1, and the collector-emitter of atransistor T-2 to the devices 24 and 26 of the antilog circuit.

The base of the transistor T-l is connected to bus 8 through theresistor R3 and diode D1 whereby the current ratio between the circuits16' and 17 is maintained. The base of the transistor T-2 is connected tothe common point between the resistor R4 and Zener diode D2 whereby thesubstantially constant voltage established by the diode D2 will maintaina substantially constant potential across the antilog circuit 22. Thefilter network Fl also includes capacitors C2 and C3 and is effectivewhen switch SW1 is in its illustrated or a position to cause the entirealternating component of the current flowing in the antilog circuit 22to circulate through the device 24 with only the DC component flowingthrough the device 26, shunt S1 and instrument 21. The filter network Flpermits the use of capacitors C2 and C3 having a much lower capacitancethan that required by the capacitor 28 in FIG. 1.

With switch SW1 in its other or b position the filter network F1 is nolonger effective to prevent the flow of the alternating componentthrough the device 26 and this alternating component flows through bothdevices 24 and 26. Under this condition the instrument or meter 21 willindicate the average rather than the RMS value of the input quantity tothe transformer 1A. This is somewhat like the circuit shown in FIG. 6 ofUS. Pat. No. 3,152,250 to G. E. Platzer, Jr.

That the meter 21 will be energized with the quantity directlyproportional to the average value of the input quantity is shownby thefollowing mathematical treatment in which like designations representlike quantities to those set forth in the preceding mathematicaltreatment of FIG. 1.

g (KBK4F):IOg(K1 2 (19) K K i K, K x (2 K K, x /lr K. 21)

F r z/ a 4) (22) i K2 x 23 =f( (In n +f( H0) (25) T 1 T 1 n+1 1f ma -Kram (26) T 1 I f0 T (MP0 (14) by definition T 1 d J; -,f(t) t-a: average(27) therefore i Kx average (28) A switch SW2 may be closed to short outthe shunt or resistor S1 as desired.

It will, therefore, be apparent that there has been disclosed aninexpensive simple RMS transducer wherein p of said first paths beingcharacterized by the fact that the voltage established across said firstpath is proportional to the log of the current flow through said firstpath, the magnitude of the proportion and of the base of the log of allof said devices being substantially identical, control means energizedby the sum of the magnitudes of said established voltage of said firstpaths of said first series circuit, said control means being coupled tosaid second series circuit for regulating the current through saidsecond series circuit as the antilog function of the sum of themagnitudes of said established voltages of said first paths of saidfirst series cir cuit, and shunting means associated with one of saiddevices of said second series circuit for shunting around its said firstpath the alternating component of the current through said second seriescircuit.

2. The combination of claim 1 in which said first and second and thirddevices are solid state devices operating as diodes, said fourth deviceis a solid state triode, and said control means is connected to saidfourth device.

3. The combination of claim 2 in which said sum of the magnitudes ofsaid logs is an electrical voltage, and in which said devices of saidsecond series circuit are arranged such that any current flow caused bysaid voltage flows through both of said devices of said second circuit.

4. The combination of claim 3 in which all of said devices aretransistors and in which said shunting means is a capacitor.

5. The combination of claim 4 in which a source of unidirectionalpotential is connected to energize said second circuit, and a directcurrent sensing instrument is connected to respond to the flow of directcurrent through said second circuit.

6. The combination of claim 5 in which there is provided a full waverectifier and a transformer, said transformer being connected to saidinput terminals through said rectifier.

7. A transducer providing a unidirectional electrical quantityproportional to the RMS value of a pulsating quantity, said transducercomprising a pair of input terminals for energization by said pulsatingquantity, a plurality of current flow devices having a current paththerethrough, each of said devices being characterized by the fact thatthe current flow through its said path establishes a first controlquantity which is proportional to the log of the current therethrough,the proportion and the base of the log of all of said devices beingsubstantially identical, means connecting said paths of a first and asecond of said devices to provide a first series circuit connected tosaid input terminals, second means connecting said path of a third and afourth of said devices to provide a second series circuit, current flowcontrolling means controlling the current flow through said secondseries circuit in accordance with the magnitude of a second controlquantity supplied thereto, means connecting said current flowcontrolling means to said first series circuit for energization thereofby the magnitude of the sum of said first quantities of said first andsecond devices, the magnitude of said second control quantity beingproportional to the magnitude of said sum, and means preventing the flowof the alternating current component, of the current in said.

8. The combination of claim 7 in which said pulsating quantity is analternating quantity, a rectifier means is interposed between said inputterminals and said first series circuit, said rectifier means beingeffective to permit current flow through said first series circuitsolely in a first direction, and in which there is provided a source ofunidirectional potential for current flow through said second seriescircuit.

9. The combination of claim 8 in which said third device is a solidstate triode comprising a main path including its said first path and acontrol path including its said first path, said second series circuitincluding said main path, said current flow controlling means includingsaid control path.

10. The combination of claim 9 in which said means which prevents theflow of the alternating component is a capacitor connected in parallelwith said current path of said one device.

11. The combination of claim 10 in which said one device is said thirddevice.

12. The combination of claim 10 in which said one device is said fourthdevice.

13. In combination, first and second and third current conductingdevices, each of said devices having a main circuit and characterized bythe fact that the voltage developed across said device of its said maincircuit is substantially proportional to the log of the current flowingthrough its said main circuit, a fourth regulated current conductingdevice having a main circuit and a control circuit which controls themagnitude of the current flowing in said main circuit as a function ofthe magnitude of a first electrical quantity applied to said controlcircuit, each said circuit of said fourth device being characterized bythe fact that the voltage developed thereacross is substantiallyproportional to the log of the current flowing therethrough, input meansadapted to supply a rectified quantity to said first current conductingdevice whereby unidirectional current flows through said first device inaccordance with the instantaneous magnitude of said sinusoidal quantity,input means adapted to supply a rectified quantity to said secondcurrent conducting device whereby current flows through said seconddevice in accordance with the instantaneous magnitude of the saidquantity applied thereto, a circuit means connected to said first andsecond devices and connected to said control circuitof said fourthdevice, said last named circuit means being effective to energize saidcontrol circuit with said first signal at a magnitude which is afunction of the sum of the magnitudes of the potentials which appearacross said first and second devices, an output circuit comprising theseries connection of said main circuits of said third and fourthdevices, and means eliminating the alternating current component of thecurrent in said output circuit from one of said-main circuits of saidoutput circuit.

14. The combination of claim 13 in which said means which eliminates theflow of the alternating current component is a capacitor connected inshunt with said one main circuit.

15. The combination of claim 14 in which said devices each include a p-nsemiconductorjunction to provide said voltage developed thereacross.

16. The combination of claim 15 in which said p-n junction of saidfourth device is located in each of its said circuits.

17. The combination of claim 13 in which each of said devices is atransistor, each said transistor includes a base and a collector and anemitter, said first and said second and third devices each having theirsaid base connected to their said collectors. I

'18. The combination of claim 15 in which all of said p-n junctionsprovide substantially the same log value with respect to the currentflow therethrough.

19. The combination of claim 13 in which there is provided a source ofunidirectional potential for said output circuit, said means whicheliminates the flow of the alternating current component comprises aresistor capacitor network comprising at least a pair of capacitors anda pair of resistors, said resistors being connected in series andbetween a selected main circuit of said output circuit and said sourceof potential, a first of said capacitors being connected between acommon connection of said resistors and a first point in said outputcircuit, a second of said capacitors being connected between the commonconnection of said resistors and said selected main circuit and saidfirst point.

20. The combination of claim 19 in which a load device is connected intosaid output circuit intermediate said resistors and said source ofpotential, and in which locating means selectively determines thelocation of said first point in said output circuit.

21. The combination of claim 20 in which said locating means in a firstcondition determines the location of said first point to be intermediatesaid main circuits of said output circuit and in a second conditiondetermines said first point to be intermediate said load device and saidsource of potential.

22. A transducer comprising a current transformer having outputterminals; a full wave rectifying network having alternating currentinput terminals connected to said transformer output terminals; saidnetwork having direct current output terminals; a network having firstand second paths connected between said direct current terminals; saidfirst path including in series circuit and in the order named, a firstresistor, the p-n junction of a first device, and a log quantityestablishing network comprising the p-n junctions of second and thirddevices; said second path including in series circuit and in the ordernamed a second and third resistor and a first voltage determiningelement; said second path further including a second voltage determiningelement in par allel with said second resistor and said first voltagedetermining element; a third path connected in shunt cir cuit with saidsecond voltage determining element and including in series circuit andin the order names a load device, the p-n junction of a fourth deviceand an antilog quantity establishing network comprising the p-njunctions of a fifth and a sixth device; means connecting a controlelectrode of said first device to the common connection between saidsecond and said third resistors; means connecting the control electrodeof said fourth device the common connection of said third resistor andsaid first voltage determining element; and means connecting the controlelectrode of said fifth device to the common connection of said firstdevice and said p-n junction of said second device.

23. The combination of claim 22 which includes a capacitive networkconnected in parallel with at least one p-n junction of said third path.

24. The combination of claim 22 which includes a capacitive networkconnected in parallel with the p-n junction of said fourth and saidfifth devices.

25. The combination of claim 22 which includes an alternating currentconducting network, and means selectively connecting said alternatingcurrent network in parallel with the p-n junctions of said fourth andfifth devices and in parallel with said load device.

26. The combination of claim 24 in which said capacitive networkincludes fourth and fifth resistors and first and second capacitors,said fourth and fifth resistors being connected in series in said thirdpath intermediate said load device and the p-n junctions of said fourthdevice, said first capacitor being connected between the common point ofsaid fourth and fifth resistors and a first common point between the p-njunction of said fifth device and the p-n junction of said sixth device,said second capacitor being connected between the common point of one ofsaid fourth and fifth resistors and said first common point.

27. The combination of claim 26 in which means is provided to disconnectsaid capacitors from said first common point and to connect saidcapacitors to a second common point intermediate said load device andsaid second voltage determining element.

28. The combination of claim 22 in which said devices having the p-njunctions are all transistors, said control electrode of said first andsaid fourth and said fifth devices being bases of the respective saiddevices, the bases of said second and said third and said sixth devicesbeing connected to one of said collector and emitter thereof to causesaid just-named devices to operate as diodes.

1. An RMS transducer comprising a pair of input terminals, a firstseries circuit comprising first paths of first and second devicesconnected to said input terminals for energization therefrom, a secondseries circuit comprising first paths of third and fourth devices, eachof said first paths being characterized by the fact that the voltageestablished across said first path is proportional to the log of thecurrent flow through said first path, the magnitude of the proportionand of the base of the log of all of said devices being substantiallyidentical, control means energized by the sum of the magnitudes of saidestablished voltage of said first paths of said first series circuit,said control means being coupled to said second series circuit forregulating the current through said second series circuit as the antilogfunction of the sum of the magnitudes of said established voltages ofsaid first paths of said first series circuit, and shunting meansassociated with one of said devices of said second series circuit forshunting around its said first path the alternating component of thecurrent through said second series circuit.
 2. The combination of claim1 in which said first and second and third devices are solid statedevices operating as diodes, said fourth device is a solid state triode,and said control means is connected to said fourth device.
 3. Thecombination of claim 2 in which said sum of the magnitudes of said logsis an electrical voltage, and in which said devices of said secondseries circuit are arranged such that any current flow caused by saidvoltage flows through both of said devices of said second circuit. 4.The combination of claim 3 in which all of said devices are transistorsand in which said shunting means is a capacitor.
 5. The combination ofclaim 4 in which a source of unidirectional potential is connected toenergize said second circuit, and a direct current sensing instrument isconnected to respond to the flow of direct current through said secondcircuit.
 6. The combination of claim 5 in which there is provided a fullwave rectifier and a transformer, said transformer being connected tosaid input terminals through said rectifier.
 7. A transducer providing aunidirectional electrical quantity proportional to the RMS value of apulsating quantity, said transducer comprising a pair of input terminalsfor energization by said pulsating quantity, a plurality of current flowdevices having a current path therethrough, each of said devices beingcharacterized by the fact that the current flow through its said pathestablishes a first control quantity which is proportional to the log ofthe current therethrough, the proportion and the base of the log of allof said devices being substantially identical, means connecting saidpaths of a first and a second of said devices to provide a first seriescircuit connected to said input terminals, second means connecting saidpath of a third and a fourth of said devices to provide a second seriescircuit, current flow controlling means controlling the current flowthrough said second series circuit in accordance with the magnitude of asecond control quantity supplied thereto, means connecting said currentflow controlling means to said first series circuit for energizationthereof by the magnitude of the sum of said first quantities of saidfirst and second devices, the magnitude of said second control quantitybeing proportional to the magnitude of said sum, and means preventingthe flow of the alternating current component, of the current in saidsecond series circuit, through said path of one of said deviCes of saidsecond series circuit.
 8. The combination of claim 7 in which saidpulsating quantity is an alternating quantity, a rectifier means isinterposed between said input terminals and said first series circuit,said rectifier means being effective to permit current flow through saidfirst series circuit solely in a first direction, and in which there isprovided a source of unidirectional potential for current flow throughsaid second series circuit.
 9. The combination of claim 8 in which saidthird device is a solid state triode comprising a main path includingits said first path and a control path including its said first path,said second series circuit including said main path, said current flowcontrolling means including said control path.
 10. The combination ofclaim 9 in which said means which prevents the flow of the alternatingcomponent is a capacitor connected in parallel with said current path ofsaid one device.
 11. The combination of claim 10 in which said onedevice is said third device.
 12. The combination of claim 10 in whichsaid one device is said fourth device.
 13. In combination, first andsecond and third current conducting devices, each of said devices havinga main circuit and characterized by the fact that the voltage developedacross said device of its said main circuit is substantiallyproportional to the log of the current flowing through its said maincircuit, a fourth regulated current conducting device having a maincircuit and a control circuit which controls the magnitude of thecurrent flowing in said main circuit as a function of the magnitude of afirst electrical quantity applied to said control circuit, each saidcircuit of said fourth device being characterized by the fact that thevoltage developed thereacross is substantially proportional to the logof the current flowing therethrough, input means adapted to supply arectified quantity to said first current conducting device wherebyunidirectional current flows through said first device in accordancewith the instantaneous magnitude of said sinusoidal quantity, inputmeans adapted to supply a rectified quantity to said second currentconducting device whereby current flows through said second device inaccordance with the instantaneous magnitude of the said quantity appliedthereto, a circuit means connected to said first and second devices andconnected to said control circuit of said fourth device, said last namedcircuit means being effective to energize said control circuit with saidfirst signal at a magnitude which is a function of the sum of themagnitudes of the potentials which appear across said first and seconddevices, an output circuit comprising the series connection of said maincircuits of said third and fourth devices, and means eliminating thealternating current component of the current in said output circuit fromone of said main circuits of said output circuit.
 14. The combination ofclaim 13 in which said means which eliminates the flow of thealternating current component is a capacitor connected in shunt withsaid one main circuit.
 15. The combination of claim 14 in which saiddevices each include a p-n semiconductor junction to provide saidvoltage developed thereacross.
 16. The combination of claim 15 in whichsaid p-n junction of said fourth device is located in each of its saidcircuits.
 17. The combination of claim 13 in which each of said devicesis a transistor, each said transistor includes a base and a collectorand an emitter, said first and said second and third devices each havingtheir said base connected to their said collectors.
 18. The combinationof claim 15 in which all of said p-n junctions provide substantially thesame log value with respect to the current flow therethrough.
 19. Thecombination of claim 13 in which there is provided a source ofunidirectional potential for said output circuit, said means whicheliminates the flow of the alternating current component comprises aresistor capacitor network comprising at least a pair of capacitors anda pair of resistors, said resistors being connected in series andbetween a selected main circuit of said output circuit and said sourceof potential, a first of said capacitors being connected between acommon connection of said resistors and a first point in said outputcircuit, a second of said capacitors being connected between the commonconnection of said resistors and said selected main circuit and saidfirst point.
 20. The combination of claim 19 in which a load device isconnected into said output circuit intermediate said resistors and saidsource of potential, and in which locating means selectively determinesthe location of said first point in said output circuit.
 21. Thecombination of claim 20 in which said locating means in a firstcondition determines the location of said first point to be intermediatesaid main circuits of said output circuit and in a second conditiondetermines said first point to be intermediate said load device and saidsource of potential.
 22. A transducer comprising a current transformerhaving output terminals; a full wave rectifying network havingalternating current input terminals connected to said transformer outputterminals; said network having direct current output terminals; anetwork having first and second paths connected between said directcurrent terminals; said first path including in series circuit and inthe order named, a first resistor, the p-n junction of a first device,and a log quantity establishing network comprising the p-n junctions ofsecond and third devices; said second path including in series circuitand in the order named a second and third resistor and a first voltagedetermining element; said second path further including a second voltagedetermining element in parallel with said second resistor and said firstvoltage determining element; a third path connected in shunt circuitwith said second voltage determining element and including in seriescircuit and in the order names a load device, the p-n junction of afourth device and an anti-log quantity establishing network comprisingthe p-n junctions of a fifth and a sixth device; means connecting acontrol electrode of said first device to the common connection betweensaid second and said third resistors; means connecting the controlelectrode of said fourth device the common connection of said thirdresistor and said first voltage determining element; and meansconnecting the control electrode of said fifth device to the commonconnection of said first device and said p-n junction of said seconddevice.
 23. The combination of claim 22 which includes a capacitivenetwork connected in parallel with at least one p-n junction of saidthird path.
 24. The combination of claim 22 which includes a capacitivenetwork connected in parallel with the p-n junction of said fourth andsaid fifth devices.
 25. The combination of claim 22 which includes analternating current conducting network, and means selectively connectingsaid alternating current network in parallel with the p-n junctions ofsaid fourth and fifth devices and in parallel with said load device. 26.The combination of claim 24 in which said capacitive network includesfourth and fifth resistors and first and second capacitors, said fourthand fifth resistors being connected in series in said third pathintermediate said load device and the p-n junctions of said fourthdevice, said first capacitor being connected between the common point ofsaid fourth and fifth resistors and a first common point between the p-njunction of said fifth device and the p-n junction of said sixth device,said second capacitor being connected between the common point of one ofsaid fourth and fifth resistors and said first common point.
 27. Thecombination of claim 26 in which means is provided to disconnect saidcapacitors from said first common point and to connect said capacitorsto a second common point intermediate said load device and said seconDvoltage determining element.
 28. The combination of claim 22 in whichsaid devices having the p-n junctions are all transistors, said controlelectrode of said first and said fourth and said fifth devices beingbases of the respective said devices, the bases of said second and saidthird and said sixth devices being connected to one of said collectorand emitter thereof to cause said just-named devices to operate asdiodes.